Accuracy Configurable Adder Based On The Conventional Cla

Abstract

The speed and power consumption of a digital signal processing (DSP) system are directly related to the adder, an essential arithmetic module. Due to the requirements for high speed, power efficiency, approximate adders have been created. In error-tolerant applications like multimedia processing, machine learning, and many others, approximate computing is a potent technique for lowering energy consumption and computational delay. In these circumstances, designing effective digital data-paths is of utmost importance. The addition operation has therefore received a lot of attention. The majority of the earlier approximate adders, though, were made for Application Specific Integrated Circuits (ASICs), so it seems impossible to use them with other hardware, like Field Programmable Gate Arrays (FPGAs) (or at least ineffective). This paper describes a brand-new approximate addition method that makes use of an FPGA device's configurable resources. In this paper, anCarry maskable approximate adder without the cost of increased power consumption or delay for configurability was proposed. The conventional CLA serves as the foundation for the proposed adder, and runtime accuracy configuration is accomplished by masking carry propagation. In comparison to the traditional CLA, the proposed adder speeds up with a small area overhead, according to the experimental results.